Availability · 1990
Placed by the contemporary primary publication. The exact event date is not known; its documented interval appears below.
Neural network chips from Intel and Adaptive Solutions
In 1989-1990 two chips appeared that were made for neural networks. Intel's analog ETANN had 64 neurons and 10,240 synapses, its weights held as charge on floating gates, and computed more than 1.3 billion connections a second. Adaptive Solutions' digital CNAPS had 64 processors at 25 MHz and learned on the chip itself.
Why it matters
A neural network became not only a program on a general-purpose machine but a separate product of two companies. The two chips showed at once both paths the line kept choosing between: analog density with limited precision against digital flexibility with learning on the chip.
ETANN, by its Intel designers' 1993 abstract: a 1-micron CMOS non-volatile memory process, a 64 x 64 EEPROM weight array, more than 1.3 billion connections a second, and more than 2 billion in a 2:1 multiplex mode. Users of the chip in 1992 (an AFIT thesis working from Intel's manual, and a Fermilab report) write that weights are retained for at least 10 years and that learning is mostly done off the chip; one gives a weight resolution of 7.5 bits, the other about 6.
CNAPS, by Adaptive Solutions' NIPS 1990 paper: all processors receive the same instruction, 1.6 billion inner product steps a second per chip, a 9 x 16-bit multiplier, 16-bit weights. An eight-chip board updates 2.3 billion connections a second in learning and processes 9.6 billion in the forward pass, but these figures come from a clock-accurate simulator, not measured silicon.
What the record does not claim: that these were the first commercial neural network chips, or the month ETANN was shown; neither the 1989 paper nor Intel's data sheet could be read.
Event record
- Event date
- 1989 – 1990
- Timeline date
- Primary publication date
- Verification
- Sources gathered automatically · September 27, 2026
- Lines
- ID
- evt-0866
Intel presented ETANN at IJCNN 1989 in Washington, per Crossref and a citation in the Fermilab report; no document read gives the month. Hammerstrom presented the CNAPS architecture at IJCNN in San Diego on 17-21 June 1990, per Crossref; Adaptive Solutions' paper on back-propagation on CNAPS is in the NIPS 1990 proceedings.
Sources
- primary Implementation and performance of an analog nonvolatile neural network (Hernan A. Castro, Simon M. Tam, Mark A. Holler), Analog Integrated Circuits and Signal Processing 4(2), 97 ff., September 1993: abstract
Springer (Kluwer Academic Publishers) · Published September 1993
- primary Back Propagation Implementation on the Adaptive Solutions CNAPS Neurocomputer Chip (Hal McCartor, Adaptive Solutions Inc.), Advances in Neural Information Processing Systems 3 (NIPS 1990), 1028-1031
Morgan Kaufmann (NeurIPS proceedings site) · Published 1990
- secondary ETANN Hardware Implementation for Radar Emitter Identification (James B. Calvin, Jr.), Air Force Institute of Technology thesis AFIT/GE/ENG/92D-08, December 1992 (DTIC AD-A259 077)
Air Force Institute of Technology (DTIC copy in the Internet Archive) · Published December 1992
- secondary A Study of the Intel ETANN VLSI Neural Network for an Electron Isolation Trigger (Clark S. Lindsey, Bruce Denby), FERMILAB-TM-1798, October 1992
Fermi National Accelerator Laboratory · Published October 1992
Related events
- Related Mead names neuromorphic systems
ETANN stores its weights as analog charge on floating gates, the mechanism Mead in 1990 calls a natural analog memory.
- Related Google's Tensor Processing Unit
CNAPS and the TPU are both digital chips that multiply network weights in integers of limited width, a quarter of a century apart.
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