Hardware before the TPU

What was missing

The compute line had seventy records in the 2020s and fifteen in the 2010s. Between SNARC in 1951 and the GeForce 256 in 1999 there were only four. The 2016 TPU is a systolic array, but the word systolic did not occur in the atlas, so the TPU record stood without a predecessor. The direction the 6-in-1 set, prehistory over the fresh tail, meant filling exactly this middle.

Nine records

The Mark I Perceptron had a retina of 20 x 20 photoresistors and 512 association units, and its weights were potentiometers turned by electric motors. By March 1960 its engineers were already presenting it at the IRE convention. In August 1977 the authors of the MIT Lisp machine called it a personal computer whose instruction set was designed for Lisp. Next come Kung and Leiserson’s systolic arrays of 1978. They are what Google’s TPU paper cites when it explains why its matrix unit is systolic. Warp, Carnegie Mellon’s systolic machine of 1986, rode in the Navlab van, and the ALVINN network was trained on it. The other records are WISARD, with 32,000 memory chips in place of neurons; Hsu’s chess chip, which led through Deep Thought to the 480 chips of Deep Blue; Mead’s neuromorphic systems of 1990; the ETANN and CNAPS chips; and the ANNA chip, on which a Bell Labs convolutional network ran in 1991.

As in Request 1, the hypotheses about dates and figures were written before any source was opened. Five dates of ten matched and one was wrong: the WISARD article appeared in March 1984, not July. Three hypothesised figures failed. WISARD did not deliver 25 frames a second; it took 5-10 decisions a second. ETANN computed over 1.3 billion connections a second, and reached two billion only in a multiplexed mode. The Lisp machine prototype was not running from 1976: it got memory and a disk only at the beginning of 1977.

Where the brief was wrong

Five items of the brief said more than the documents. The Mark I did not yet exist in 1958. No one claims it was the first machine built for an AI language. No document read describes WISARD recognising faces in real time. ALVINN was trained on Warp but drove on the on-board Sun. No one proclaims the first commercial neural network chips either. The 1989-1990 papers on ETANN and CNAPS could not be read, because IEEE Xplore does not answer a cloud session. So the two chips share one record at medium confidence.

The axis data budget was raised as the first action. After the package the tightest page is the axis document itself, with 758 bytes to spare.